1. Field of Invention
This invention relates generally to the growth of III-nitride films on mismatched substrates.
2. Description of Related Art
Semiconductor light-emitting devices (LEDs) are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness LEDs capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, or III-nitride substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, a light emitting or active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region.
Since III-nitride substrates are generally not commercially available, III-nitride devices are often fabricated on substrates such as sapphire and SiC, which are referred to as “mismatched” because of differences in lattice constant and thermal expansion coefficients between these substrates and III-nitride layers. The differences in lattice constant and thermal expansion coefficient cause strain which makes the fabrication of thick, flat, defect-free III-nitride layers difficult.
In the case of sapphire substrates in particular, one method to alleviate the problems caused by the lattice constant and thermal expansion coefficient mismatch is to grow the III-nitride device layers on a nucleation layer grown over the substrate. The nucleation layer is usually a thin amorphous or polycrystalline AIN or GaN layer formed by low temperature growth. In theory, since the amorphous or polycrystalline nucleation layer alleviates some strain caused by the lattice constant and thermal expansion coefficient mismatch, the quality of a crystalline III-nitride layer grown over the nucleation layer should be improved over a III-nitride layer grown without a nucleation layer.
The use of low temperature nucleation layers is not ideal for several reasons. Before growth of the semiconductor layers, the substrate is heated to a high temperature for cleaning, then the temperature in the reactor is reduced to grow the low temperature nucleation layer. The temperature must then be raised again to grow the device layers. Such temperature cycling is time consuming and therefore increases the likelihood of the accumulation of contaminants on the wafer surface that can affect yield or device performance. In addition, the heating that takes place between growth of the low temperature nucleation layer and growth of the next layer causes recrystallization in the low temperature nucleation layer that is necessary for growth of high quality layers over the nucleation layer. Accordingly, the heating must be carefully controlled. Deviations from the desired heating pattern can cause poor device performance or poor yields. Further, the materials quality of layers grown over the low temperature nucleation layer and the performance of the resulting device is sensitive to the thickness of the nucleation layer and the growth temperature of the nucleation layer. The thickness and temperature regimes that yield acceptable device performance can be narrow, making it difficult to maintain the required thickness and temperature regimes across the wafer and resulting in poor yield. Finally, employing a low temperature nucleation layer results in a high density of threading dislocations in the device layers, on the order of 1010 cm−2. Additional processing is required to reduce the density of the threading dislocations. Such additional processing increases the time and cost of fabrication and the risk of poor yield or poor device performance.
Another method to alleviate the problems caused by the lattice constant and thermal expansion coefficient mismatch is described by U.S. Pat. No. 5,990,495 to Ohba. Ohba teaches “growing a buffer layer directly on a monocrystal substrate at a first temperature . . . and growing an element-forming layer on said buffer layer at a second temperature which is lower than said first temperature . . . . The temperature for growing the buffer layer should preferably be higher than 1300° C.” See column 3, lines 54-64. After growth, the nucleation layer is annealed. “The temperature for annealing the buffer layer is preferably in the range of 1350° C. to 1500° C., and the time period for annealing the buffer layer should preferably be in the range of 10 minutes to 60 minutes. If the annealing temperature is less than 1350° C., it would be difficult to alleviate strain completely.” See column 6, line 64 to column 7, line 2. Ohba's method of fabricating a high temperature nucleation layer is undesirable because it requires high temperature growth and a growth pause in order to perform the anneal.